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<div class="title">xrgb2ycrcb_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga6674d0052e35ad32c02a773a39deb844"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rgb2ycrcb__v7__0.html#ga6674d0052e35ad32c02a773a39deb844">XRgb2YCrCb_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__rgb2ycrcb__v7__0.html#ga4daefbb12305f488581147b0944637d7">XRgb2YCrCb_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="separator:ga6674d0052e35ad32c02a773a39deb844"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a37cc9c43e6dae7a2ded7ccb97050ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rgb2ycrcb__v7__0.html#ga5a37cc9c43e6dae7a2ded7ccb97050ac">XRgb2YCrCb_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__rgb2ycrcb__v7__0.html#ga878aefddd360571d05e260f065210552">XRgb2YCrCb_Out32</a>((BaseAddress) + (u32)(RegOffset),(u32)(Data))</td></tr>
<tr class="separator:ga5a37cc9c43e6dae7a2ded7ccb97050ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Control registers offset for RGB2YCRCB core. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Timing Control Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Timing control registers offset for RGB2YCRCB core. </p>
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<tr><td colspan="2"><div class="groupHeader">Core Specific Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Core specific registers offset. </p>
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<tr><td colspan="2"><div class="groupHeader">Control Register Bit Masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Control Register bit definition for RGB2YCRCB core. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Error Bit Masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Register Bit Masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Interrupt Register bit definition for RGB2YCRCB core.</p>
<p>It is applicable for STATUS and IRQ_ENABLE Registers. </p>
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<tr><td colspan="2"><div class="groupHeader">Version Register Bit Masks and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Version Register bit definition for RGB2YCRCB core. </p>
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<tr><td colspan="2"><div class="groupHeader">ActiveSize Register Bit Masks and Shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">YMax Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">YMin Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CBMax Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CBMin Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CRMax Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CRMin Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">YOffset Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CbOffset Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CrOffset Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">ACOEF, BCOEF, CCOEF, DCOEF Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">General purpose Bit Mask and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Data widths in bits per color.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Backward Compatibility Macros</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>To support backward compatibility, following macro definitions are re-defined. </p>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Interrupt status register generates a interrupt if the corresponding bits of interrupt enable register bits are set. </p>
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